1. Field of the Invention
Embodiments of the invention relate to memory devices, and more particularly, in one or more embodiments, to flash memory devices.
2. Description of the Related Art
Flash memory devices are non-volatile memory devices which store information on a semiconductor in a way that needs no power to maintain the information stored therein. Flash memory devices have been widely used as mass-storage devices because of their high storage densities and low costs.
Referring to FIG. 1, a conventional NAND flash memory device includes a memory block 100. The illustrated memory block 100 includes a plurality of memory cells arranged in a matrix form. The memory block 100 also includes first to m-th data lines, such as bit lines BL0-BLM, and first to n-th access lines, such as word lines WL0-WLN. In some arrangements, m can be 32,767 or 65,535, and n can be 32 or 64. The bit lines BL0-BLM extend parallel to one another in a column direction. The word lines WL0-WLN extend parallel to one another in a row direction perpendicular to the column direction. The memory block 100 also includes upper and lower bit line select transistors 120a, 120b for selecting the memory block 100.
Each bit line includes a string of memory cells 110. For example, the second bit line BL1 is coupled to memory cells 110 connected in series. Each of the memory cells 110 includes a floating gate transistor. The floating gate transistors are coupled to one another in series from source to drain. The control gates of the floating gate transistors of the memory cells 110 of a common row are coupled to the same word line (in certain arrangements, the control gates and portions of the word lines can be the same structure). Each of the memory cells 110 stores a charge (or a lack of charge). The amount of stored charge can be used to represent, for example, one or more states, which can represent one or more digits (for example, bits) of data. The memory cells 110 can be either a single-level cell (SLC) or a multi-level cell (MLC). A charge stored in a floating gate transistor sets the threshold voltage of the floating gate transistor. Thus, the amount of a charge in the floating gate transistor of a memory cell 110 may be determined by sensing the threshold voltage of the floating gate transistor.
FIG. 2 illustrates a cross-section of the floating gate transistors of the memory cells 110 in the second bit line BL1. The floating gate transistors are formed on a substrate 201. Each of the floating gate transistors includes a source region 210 (which can be a drain region for a neighboring transistor of the same bit line), a drain region 212 (which can be a source region for a neighboring transistor of the same bit line), a doped channel region 214, a first dielectric 216 (for example, a tunnel oxide), a floating gate 218, a second dielectric 220 (for example, a gate oxide, wherein the tunnel and gate oxide can be formed of the same or different material), and a control gate/word line 222. The first dielectric 216 is formed on the channel region 214 to insulate the floating gate 218 from the channel region 214. The second dielectric 220 physically and electrically separates the floating gate 218 from the control gate 222. The control gate 222 is coupled to (e.g., forms) an appropriate word line, for example, word line WL1. Electrons can be trapped on the floating gate 218 and be used to store data.
During a write operation of the NAND flash memory device, data is typically written on a group of memory cells coupled to a single word line. Such a group of memory cells can be referred to as a “page.” In one arrangement, a page may include all memory cells coupled to a word line. In other arrangements, a page may be formed by every other memory cells coupled to a single word line. In certain arrangements, a page may be formed by every fourth memory cells coupled to a single word line. It will be understood that a page may be formed by any suitable selected number of memory cells coupled to a word line.
In certain instances, memory cells in a block are erased to have the same data as one another. Typically, an erase operation is performed on a block basis. For example, each of single-level memory cells in a memory block can store a data bit, either “0” or “1,” in a programmed state. Ideally, all of the memory cells may have 1's in an erased state. Similarly, each of multi-level memory cells in a memory block may store one of multiple data values, for example, 11, 01, 10, 11 in four-level cells in a programmed state. Ideally, all of the multi-level memory cells may have, for example, “11” in an erased state.
However, in practice, some of memory cells in a memory block may not be fully erased after an erase operation. Such memory cells adversely affect the accuracy of data stored in the memory cells. Thus, NAND flash memory devices typically use an erase verification scheme after an erase operation to determine if there are unerased memory cells. If there are unerased memory cells, the entire memory block may be re-erased.
Referring to FIG. 3A, a conventional erase-verification method will be described in the following. FIG. 3A illustrates a portion of a NAND flash memory device. The portion includes a string of memory cells C0-Cn coupled to a bit line (hereinafter, referred to as a NAND string NS), upper and lower bit line select transistors 120a, 120b, and a current source 130. In the method, the whole NAND string NS is erase-verified at a time. The gates of the upper and lower bit line select transistors 120a, 120b are provided with Vsgd and Vsgs, respectively, and the gates of all the memory cells C0-Cn are provided with a word line voltage VgWL. For example, each of Vsgd and Vsgs is about 3 V and VgWL is about 0 V. By applying 3 V to the bit line select transistors 120a, 120b, the bit line select transistors 120a, 120b are fully turned on.
The resulting circuit formed by the NAND string NS and the current source 130 is a source-follower circuit. A typical source-follower circuit, as shown in FIG. 3C, includes a transistor Tr and a current source Is. The relationship between voltages at nodes in the source-follower circuit is represented by Equation 1 below.Vs=Vg−Vt  (1)
In Equation 1, Vs is the source voltage of the transistor Tr, Vg is the gate voltage of the transistor Tr, and Vt is the threshold voltage of the transistor Tr. VD is the drain voltage of the transistor Tr. Similarly, in the circuit formed by the NAND string NS and the current source 130 shown in FIG. 3A, the relationship between voltages at nodes in the circuit can be represented by Equation 2 below:VBL=VgWL−Vt  (2)
In Equation 2, VBL is a voltage level at a node 140 between the upper bit line select transistor 120a and the current source 130. Vt is an average threshold voltage of the memory cells C0-Cn of the NAND string NS. Because VgWL is set to 0 V in FIG. 3A, the average threshold voltage Vt can be determined by detecting the voltage level VBL at the node 140.
If substantially all of the memory cells C0-Cn of the NAND string NS have the same threshold voltage (for example, −2 V), as shown in FIG. 3A, the average threshold voltage Vt will correctly reflect the status of the memory cells. However, in practice, the average threshold voltage Vt may not fully reflect individual memory cells' status. Thus, there can be unerased cells in the NAND string NS even if the average threshold voltage Vt indicates that all the memory cells have been erased. For example, as shown in FIG. 3B, there can be unerased memory cells (for example, Cn−1 in FIG. 3B), but the average threshold voltage Vt may nevertheless indicate that all the memory cells have been fully erased.